Verification of asynchronous circuits based on zero-suppressed BDDs

Asynchronous circuits, which have no global clocks and work based on the causality relation between signal transitions, potentially have the advantages of high performance and low power dissipation. However, the state spaces of asynchronous circuits are often huge, because unlike synchronous circuits every wire has states. Thus, the formal verification of asynchronous circuits is more difficult than that of synchronous ones. In this paper, in order to reduce the computational cost of the verification, we propose implementing the trace theoretic verification by using Zero-Suppressed BDDs. The paper also shows several techniques for the performance improvement such as modeling circuits by Petri nets with inhibitor arcs, composing circuit components that do not cause safety failure, and using special ZBDD operations for Petri nets. Finally, we show some experimental results.